Hierarchical memory systems for computers typically comprise memory levels having single data ports. Each level is accessed for reading or writing through a common data bus. Lower levels of the hierarchy (those closest to the computer processor) generally are faster but are of limited data capacity compared to higher levels of the hierarchy. Thus, the lowest level, for example, contains only a fraction of all the data that might be required to perform a given computer task. By proper management of the data which is retained at the lowest level at a given time, however, many of the memory accesses are made to the data stored therein.
Occasionally, access is required to data which is not present in the lowest level. It is sometimes necessary, when this happens, to "cast out" some of the old data in the lowest level to make available storage space for the newly required data. The new data must be brought into the lowest level after the old data has been cast out and stored in a higher memory level. There is normally only one data bus for accomplishing data transfers between memory levels and with the processor. Consequently, each level must contend for access to the bus in succession with the result that system performance is reduced and the design of the level controllers is made more complicated.
Memory arrays (corresponding to a single memory level in the above discussion) are known in which a plurality of data ports are provided whereby data may be read from one array location and written into another location in the same array during the same memory cycle. Such an arrangement is taught in the U.S. Pat. No. 4,125,877, issued to John R. Reinert on Nov. 14, 1978. However, no mention is made of memory hierarchies, much less how contention for use of a single data bus might be minimized in such an environment.
U.S. Pat. Nos. 3,806,888 and 4,020,466 disclose hierarchical memory systems, the former having a single data bus between levels and the latter having, in addition, an auxiliary data path for communicating to a lower level only that portion of the data of a higher level which has been changed either by addition or by modification. Generally, the transfer of data from a first level to a second level is performed only when the data store for the second level is free. Thus, neither patent teaches a solution to the problem of maximizing the speed of transferring data simultaneously to and from the same memory level.